FIGS. 8(a) and 8(b) are diagrams illustrating a prior art compound semiconductor device where FIG. 8(a) is a plan view showing a device structure of GaAs system MESFET and FIG. 8(b) is a cross-sectional view along line 8b-8b of FIG. 8(a). In the figures, reference numeral 20 designates a GaAs substrate. A GaAs buffer layer 21 is disposed on the GaAs substrate 20. A low concentration n.sup.- type GaAs semiconductor layer 22 serving as a channel layer is produced by ion implantation in the buffer layer 21. High concentration n.sup.+ type GaAs semiconductor layers 23 are produced by ion implantation at source and drain regions at both sides of the channel layer 22. A recess 24 is produced at a prescribed portion of the channel layer 22. A gate electrode 1 is disposed on the recess 24 and forms a Schottky junction. A first ion implantation region 3 as an insulating region for element separation is produced by ion implantation employing H or the like as an ion source at the entire periphery of the device region. Ohmic source and drain electrodes 2 are produced on the device region and a part of the insulating region. Here, the thick line in FIG. 8(a) shows the boundary of the metal electrodes.
The production method and the function of the device will be described.
An n.sup.- type GaAs semiconductor layer 22 of low dopant impurity concentration, above 1.times.10.sup.17 cm.sup.-3, which serves as a channel layer is produced by impurity implantation in the buffer layer 21 having a dopant impurity concentration below 1.times.10.sup.16 cm.sup.-3 produced on a GaAs semiconductor substrate 20. At the source and drain production regions sandwiching the gate production region in the n.sup.- type GaAs semiconductor layer, which serves as the channel layer, source and drain regions comprising n.sup.+ type GaAs 23 having a high dopant concentration above 3.times.10.sup.17 cm.sup.-3, are produced by ion implantation. Thereafter, insulation implantation is carried out into the entire crystal growth layers 21 and 22 at the periphery of the transistor using photoresist (not shown) as a mask, whereby first ion implantation regions 3 are produced element i.e., isolation. Thereafter, source and drain electrodes 2 are produced on the n.sup.+ type GaAs semiconductor layer 23 simultaneously, and a portion of the n.sup.- type GaAs semiconductor layer 22 is recess etched to produce a recess 24 adjusting the device characteristics by utilizing a variation in saturation current between the source and drain electrodes. Thereafter, a gate electrode 1 is produced so as to form a Schottky junction in the recess 24.
In the GaAs system MESFET having the above-described structure, the current I.sub.ds between the source and the drain is controlled by the gate voltage applied to the gate electrode 1. In addition, in the GaAs system MESFET, device isolation is achieved by employing ion implantation.
In the GaAs system MESFET device in which the device isolation is performed by ion implantation as described above, there are problems in that variations in the gate junction breakdown voltage, particularly, reductions in the gate breakdown voltage are caused by process variations such as variations in the epitaxial wafer dependent on the wafer processing and variations in the gate processing or the like. In other words, when concentration an electric field occurs, the gate breakdown voltage is dependent on the intensity of the electric field, the attachment of the Schottky junction gate electrode, a wafer (bulk) state, and the manner of formation of the insulating interface between the insulating layer and the portion of the active layer of the FET, and these vary with processing variations.
When concentration of an electric field occurs at a portion of the insulating interface between the insulating layer and the active layer of the FET dependent on these varying factors, there arises an interface leakage of a current. In a case of a recess type gate structure, because the etching rate is different between the insulating region and the active layer portion, a step due to etching is produced at the interface between the insulating region 3 and the active layer portion 2a as shown in FIG. 10(b), and when this step is fairly steep, it causes a discontinuity in the gate electrode 1 and destruction of the gate oxide film. As a result, the gate breakdown voltage is reduced so that gate destruction is likely to arise. Because of the reduction in the gate breakdown voltage the, reliability of the device is also reduced.